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256-/1024-position, digital potentiometers with maximum 1% r-tolerance error and 20-tp memory ad5291/ad5292 rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2009C2010 analog devices, inc. all rights reserved. features single-channel, 256-/1024-position resolution 20 k, 50 k, and 100 k nominal resistance maximum 1% nominal resistor tolerance error (resistor performance mode) 20-times programmable wiper memory rheostat mode temperature coefficient: 35 ppm/c voltage divider temperature coefficient: 5 ppm/c +9 v to +33 v single-supply operation 9 v to 16.5 v dual-supply operation spi-compatible serial interface wiper setting readback power-on refreshed from 20-tp memory applications mechanical potentiometer replacement instrumentation: gain and offset adjustment programmable voltage-to-current conversion programmable filters, delays, and time constants programmable power supply low resolution dac replacement sensor calibration functional block diagram a w b rdac register data serial interface sync sclk din power-on reset otp memory block v logic sdo ext_cap v dd v ss gnd ad5291/ ad5292 reset rdy 07674-001 figure 1. general description the ad5291 and ad5292 are single-channel, 256-/1024- position digital potentiometers 1 that combine industry leading variable resistor performance with nonvolatile memory (nvm) in a compact package. these devices are capable of operating across a wide voltage range, supporting both dual supply operation at 10.5 v to 16.5 v and single supply operation at +21 v to +33 v, while ensuring less than 1% end-to-end resistor tolerance error and offering 20-time programmable (20-tp) memory. the guaranteed industry leading low resistor tolerance error feature simplifies open-loop applications as well as precision calibration and tolerance matching applications. 1 the terms digital potentiometer and rdac are used interchangeably. the ad5291 and ad5292 device wiper settings are controllable through the spi digital interface. unlimited adjustments are allowed before programming the resistance value into the 20-tp memory. the ad5291 and ad5292 do not require any external voltage supply to facilitate fuse blow, and there are 20 opportunities for permanent programming. during 20-tp activation, a permanent blow fuse command freezes the wiper position (analogous to placing epoxy on a mechanical trimmer). the ad5291 and ad5292 are available in a compact 14-lead tssop package. the part is guaranteed to operate over the extended industrial temperature range of ?40c to +105c.
ad5291/ad5292 rev. d | page 2 of 32 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 electrical characteristicsad5291 .......................................... 3 resistor performance mode code range ................................. 4 electrical characteristicsad5292 .......................................... 6 resistor performance mode code range ................................. 7 interface timing specifications.................................................. 8 absolute maximum ratings.......................................................... 10 thermal resistance .................................................................... 10 esd caution................................................................................ 10 pin configuration and function descriptions........................... 11 typical performance characteristics ........................................... 12 test circuits..................................................................................... 21 theory of operation ...................................................................... 22 serial data interface................................................................... 22 shift register ............................................................................... 22 rdac register............................................................................ 22 20-tp memory ........................................................................... 23 write protection ......................................................................... 23 basic operation .......................................................................... 24 20-tp readback and spare memory status ........................... 24 shutdown mode ......................................................................... 24 resistor performance mode...................................................... 25 reset ............................................................................................. 25 sdo pin and daisy-chain operation..................................... 25 rdac architecture.................................................................... 25 programming the variable resistor......................................... 26 programming the potentiometer divider............................... 26 ext_cap capacitor.................................................................. 27 terminal voltage operating range ......................................... 27 applications information .............................................................. 28 high voltage dac...................................................................... 28 programmable voltage source with boosted output ........... 28 high accuracy dac .................................................................. 28 variable gain instrumentation amplifier .............................. 28 audio volume control .............................................................. 29 outline dimensions ....................................................................... 30 ordering guide .......................................................................... 30 revision history 9/10rev. c to rev. d changes to sdo pin and daisy-chain operation section....... 25 3/10rev. b to rev. c changes to revision history........................................................... 2 changes to figure 3 and figure 4 captions .................................. 9 3/10rev. a to rev. b changes to data sheet title ............................................................ 1 changes to general description section ...................................... 1 changes to theory of operation section.................................... 22 12/09rev. 0 to rev. a added 50 k and 100 k specifications .........................universal changes to features section............................................................ 1 changes to table 1.............................................................................3 changes to table 2.............................................................................4 added table 3 ....................................................................................5 changes to table 4.............................................................................6 changes to table 5.............................................................................7 added table 6 ....................................................................................8 change to table 7 ..............................................................................8 changes to absolute maximum rating section ........................ 10 changes table 9 .............................................................................. 11 changes to typical performance characteristics section ........ 12 changes to ordering guide .......................................................... 30 4/09revision 0: initial version
ad5291/ad5292 rev. d | page 3 of 32 specifications electrical characteristicsad5291 v dd = 21 v to 33 v, v ss = 0 v; v dd = 10.5 v to 16.5 v, v ss = ?10.5 v to ?16.5 v; v logic = 2.7 v to 5.5 v, v a = v dd , v b = v ss , ?40c < t a < +105c, unless otherwise noted. table 1. parameter symbol conditions min typ 1 max unit dc characteristicsrheostat mode resolution n 8 bits resistor differential nonlinearity 2 r-dnl r wb , v a = nc ?1 +1 lsb resistor integral nonlinearity 2 r-inl ?1 +1 lsb nominal resistor tolerance (r-perf mode) 3 ?r ab /r ab see table 2 , table 3 ?1 0.5 +1 % nominal resistor tolerance (normal mode) ?r ab /r ab 7 % resistance temperature coefficient 4 (?r ab /r ab )/?t 10 6 code = full-scale; see figure 38 35 ppm/c wiper resistance r w code= zero scale 60 100 dc characteristicspotentiometer divider mode resolution n 8 bits differential nonlinearity 5 dnl ?0.5 +0.5 lsb integral nonlinearity 5 inl ?0.5 +0.5 lsb voltage divider temperature coefficient 4 (?v w /v w )/?t 10 6 code = half-scale; see figure 41 1.5 ppm/c full-scale error v wfse code = full scale ?2 +0.25 lsb zero-scale error v wzse code = zero scale 0 2 lsb resistor terminals terminal voltage range 6 v a , v b , v w v ss v dd v capacitance a, capacitance b 4 c a , c b f = 1 mhz, measured to gnd, code = half-scale 85 pf capacitance w 4 c w f = 1 mhz, measured to gnd, code = half-scale 65 pf common-mode leakage current 4 i cm v a = v b = v w 1 na digital inputs jedec compliant input logic high 4 v ih v logic = 2.7 v to 5.5 v 2.0 v input logic low 4 v il v logic = 2.7 v to 5.5 v 0.8 v input current i il v in = 0 v or v logic 1 a input capacitance 4 c il 5 pf digital outputs (sdo and rdy) output high voltage 4 v oh r pull_up = 2.2 k to v logic v logic ? 0.4 v output low voltage 4 v ol r pull_up = 2.2 k to v logic gnd + 0.4 v v three-state leakage current ?1 +1 a output capacitance 4 c ol 5 pf power supplies single-supply power range v dd v ss = 0 v 9 33 v dual-supply power range v dd /v ss 9 16.5 v positive supply current i dd v dd /v ss = 16.5 v 0.1 2 a negative supply current i ss v dd /v ss = 16.5 v ?2 ?0.1 a logic supply range v logic 2.7 5.5 v logic supply current i logic v logic = 5 v; v ih = 5 v or v il = gnd 1 10 a otp store current 4 , 7 i logic_prog v ih = 5 v or v il = gnd 25 ma otp read current 4 , 8 i logic_fuse_read v ih = 5 v or v il = gnd 25 ma power dissipation 9 p diss v ih = 5 v or v il = gnd 8 110 w power supply rejection ratio psrr ?v dd /?v ss = 15 v 10% %/% r ab = 20 k 0.103 r ab = 50 k 0.039 r ab = 100 k 0.021
ad5291/ad5292 rev. d | page 4 of 32 parameter symbol conditions min typ 1 max unit dynamic characteristics 5 , 10 bandwidth bw ?3 db, code = half-scale khz r ab = 20 k 520 r ab = 50 k 210 r ab = 100 k 105 total harmonic distortion thd w v a = 1 v rms, v b = 0 v, f = 1 khz db r ab = 20 k ?93 r ab = 50 k ?101 r ab = 100 k ?106 v w settling time t s v a = 30 v, v b = 0 v, 0.5 lsb error band, initial code = zero scale, board capacitance = 170 pf code = full-scale, normal mode 750 ns code = full-scale, r-perf mode 2.5 s code = half-scale, normal mode s r ab = 20 k 2.5 r ab = 50 k 7 r ab = 100 k 14 code = half-scale, r-perf mode s r ab = 20 k 5 r ab = 50 k 9 r ab = 100 k 16 resistor noise density e n_wb code = half-scale, t a = 25c, 0 khz to 200 khz nv/hz r ab = 20 k 10 r ab = 50 k 18 r ab = 100 k 27 1 typical values represent av erage readings at 25c, v dd = 15 v, v ss = ?15 v, and v logic = 5 v. 2 resistor position nonlinearity error. r-inl is the deviation from an ideal value measured between the r wb at code 0x02 to code 0xff or between r wa at code 0xfd to code 0x00. r-dnl measures the relative step change from ideal between successive tap positions. the specification is guaranteed in resistor performance mode, with a wiper current of 1 ma for v a < 12 v and 1.2 ma for v a 12 v. 3 resistor performance mode (see the resistor performance mode section). the terms resistor performance mode and r-perf mode are used interchangeably. 4 guaranteed by design and characterization, not subject to production test. 5 inl and dnl are measured at v wb with the rdac configured as a potentiometer divider similar to a voltage output dac. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. 6 resistor terminal a, resistor terminal b, and resistor terminal w have no limitations on polarity with respect to each other. dual-supply operation enables ground- referenced bipolar signal adjustment. 7 different from operating current; supply curr ent for fuse program lasts approximately 550 s. 8 different from operating current; supply curr ent for fuse read la sts approximately 550 s. 9 p diss is calculated from (i dd v dd ) + (i ss v ss ) + (i logic v logic ). 10 all dynamic characteristics use v dd = 15 v, v ss = ?15 v, and v logic = 5 v. resistor performance mode code range table 2. r ab = 20 k |v dd ? v ss | = 30 v to 33 v |v dd ? v ss | = 26 v to 30 v |v dd ? v ss | = 22 v to 26 v |v dd ? v ss | = 21 v to 22 v resistor tolerance per code r wb r wa r wb r wa r wb r wa r wb r wa 1% r-tolerance from 0x5a to 0xff from 0x00 to 0xa5 from 0x7d to 0xff from 0x00 to 0x82 from 0x7d to 0xff from 0x00 to 0x82 n/a n/a 2% r-tolerance from 0x23 to 0xff from 0x00 to 0xdc from 0x2d to 0xff from 0x00 to 0xd2 from 0x23 to 0xff from 0x00 to 0xdc from 0x23 to 0xff from 0x00 to 0xdc 3% r-tolerance from 0x1e to 0xff from 0x00 to 0xe1 from 0x19 to 0xff from 0x00 to 0xe6 from 0x17 to 0xff from 0x00 to 0xe8 from 0x17 to 0xff from 0x00 to 0xe8
ad5291/ad5292 rev. d | page 5 of 32 table 3. r ab = 50 k r ab = 100 k |v dd ? v ss | = 26 v to 33 v |v dd ? v ss | = 21 v to 26 v |v dd ? v ss | = 26 v to 33 v |v dd ? v ss | = 21 v to 26 v resistor tolerance per code r wb r wa r wb r wa r wb r wa r wb r wa 1% r-tolerance from 0x2a to 0xff from 0x00 to 0xd5 from 0x37 to 0xff from 0x00 to 0xc8 from 0x1e to 0xff from 0x00 to 0xe1 from 0x14 to 0xff from 0x00 to 0xeb 2% r-tolerance from 0x11 to 0xff from 0x00 to 0xee from 0x16 to 0xff from 0x00 to 0xe9 from 0x0a to 0xff from 0x00 to 0xf5 from 0x0a to 0xff from 0x00 to 0xf5 3% r-tolerance from 0x0a to 0xff from 0x00 to 0xf5 from 0x0d to 0xff from 0x00 to 0xf2 from 0x07 to 0xff from 0x00 to 0xf8 from 0x07 to 0xff from 0x00 to 0xf8
ad5291/ad5292 rev. d | page 6 of 32 electrical characteristicsad5292 v dd = 21 v to 33 v, v ss = 0 v; v dd = 10.5 v to 16.5 v, v ss = ?10.5 v to ?16.5 v; v logic = 2.7 v to 5.5 v, v a = v dd , v b = v ss , ?40c < t a < +105c, unless otherwise noted. table 4. parameter symbol conditions min typ 1 max unit dc characteristicsrheostat mode resolution n 10 bits resistor differential nonlinearity 2 r-dnl r wb , v a = nc ?1 +1 lsb resistor integral nonlinearity 2 r-inl r ab =50 k, 100 k ?2 +2 lsb r-inl r ab =20 k , |v dd ? v ss | = 26 v to 33 v ?2 +2 lsb r-inl r ab =20 k , |v dd ? v ss | = 21 v to 26 v ?3 +3 lsb nominal resistor tolerance (r-perf mode) 3 ?r ab /r ab see table 5 and table 6 ?1 0.5 +1 % nominal resistor tolerance (normal mode) 4 ?r ab /r ab 7 % resistance temperature coefficient (?r ab /r ab )/?t 10 6 code = full scale; see figure 38 35 ppm/c wiper resistance r w code= zero scale 60 100 dc characteristicspotentiometer divider mode resolution n 10 bits differential nonlinearity 5 dnl ?1 +1 lsb integral nonlinearity 5 inl ?1.5 +1.5 lsb voltage divider temperature coefficient 4 (?v w /v w )/?t 10 6 code = half scale; see figure 41 5 ppm/c full-scale error v wfse code = full scale ?8 +1 lsb zero-scale error v wzse code = zero scale 0 8 lsb resistor terminals terminal voltage range 4 v a , v b , v w v ss v dd v capacitance a, capacitance b 6 c a , c b f = 1 mhz, measured to gnd, code = half scale 85 pf capacitance w 5 c w f = 1 mhz, measured to gnd, code = half scale 65 pf common-mode leakage current 4 i cm v a = v b = v w 1 na digital inputs jedec compliant input logic high 4 v ih v logic = 2.7 v to 5.5 v 2.0 v input logic low 4 v il v logic = 2.7 v to 5.5 v 0.8 v input current i il v in = 0 v or v logic 1 a input capacitance 4 c il 5 pf digital outputs (sdo and rdy) output high voltage 4 v oh r pull_up = 2.2 k to v logic v logic ? 0.4 v output low voltage 4 v ol r pull_up = 2.2 k to v logic gnd + 0.4 v three-state leakage current ?1 +1 a output capacitance 4 c ol 5 pf power supplies single-supply power range v dd v ss = 0 v 9 33 v dual-supply power range v dd /v ss 9 16.5 v positive supply current i dd v dd /v ss = 16.5 v 0.1 2 a negative supply current i ss v dd /v ss = 16.5 v ?2 ?0.1 a logic supply range v logic 2.7 5.5 v logic supply current i logic v logic = 5 v; v ih = 5 v or v il = gnd 1 10 a otp store current 6 , 7 i logic_prog v ih = 5 v or v il = gnd 25 ma otp read current 6 , 8 i logic_fuse_read v ih = 5 v or v il = gnd 25 ma power dissipation 9 p diss v ih = 5 v or v il = gnd 8 110 w power supply rejection ratio 6 pssr ?v dd /?v ss = 15 v 10% %/% r ab = 20 k 0.103 r ab = 50 k 0.039 r ab = 100 k 0.021
ad5291/ad5292 rev. d | page 7 of 32 parameter symbol conditions min typ 1 max unit dynamic characteristics 5 , 10 bandwidth bw ?3 db khz r ab = 20 k 520 r ab = 50 k 210 r ab = 100 k 105 total harmonic distortion thd w v a = 1 v rms, v b = 0 v, f = 1 khz db r ab = 20 k ?93 r ab = 50 k ?101 r ab = 100 k ?106 v w settling time t s v a = 30 v, v b = 0 v, 0.5 lsb error band, initial code = zero scale, board capacitance = 170 pf code = full-scale, normal mode 750 ns code = full-scale, r-perf mode 2.5 s code = half-scale, normal mode s r ab = 20 k 2.5 r ab = 50 k 7 r ab = 100 k 14 code = half-scale, r-perf mode s r ab = 20 k 5 r ab = 50 k 9 r ab = 100 k 16 resistor noise density e n_wb code = half-scale, t a = 25c, 0 khz to 200 khz nv/hz r ab = 20 k 10 r ab = 50 k 18 r ab = 100 k 27 1 typical values represent av erage readings at 25c, v dd = 15 v, v ss = ?15 v, and v logic = 5 v. 2 resistor position nonlinearity error. r-inl is the deviation from an ideal value measured between the r wb at code 0x00b to code 0x3ff or between r wa at code 0x3f3 to code 0x000. r-dnl measures the rela tive step change from ideal between successive tap positions. the specification is guarantee d in resistor performance mode, with a wiper current of 1 ma for v a < 12 v and 1.2 ma for v a 12 v. 3 resistor performance mode (see the resistor performance mode section). the terms resistor performance mode and r-perf mode are used interchangeably. 4 guaranteed by design and characterization, not subject to production test. 5 inl and dnl are measured at v w with the rdac configured as a potentiometer divider similar to a voltage output dac. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. 6 resistor terminal a, resistor terminal b, and resistor terminal w have no limitations on polarity with respect to each other. dual-supply operation enables ground- referenced bipolar signal adjustment. 7 different from operating current; supply curr ent for fuse program lasts approximately 550 s. 8 different from operating current; supply curr ent for fuse read la sts approximately 550 s. 9 p diss is calculated from (i dd v dd ) + (i ss v ss ) + (i logic v logic ). 10 all dynamic characteristics use v dd = 15 v, v ss = ?15 v, and v logic = 5 v. resistor performance mode code range table 5. r ab = 20 k |v dd ? v ss | = 30 v to 33 v |v dd ? v ss | = 26 v to 30 v |v dd ? v ss | = 22 v to 26 v |v dd ? v ss | = 21 v to 22 v resistor tolerance per code r wb r wa r wb r wa r wb r wa r wb r wa 1% r-tolerance from 0x15e to 0x3ff from 0x000 to 0x2a1 from 0x1f4 to 0x3ff from 0x000 to 0x20b from 0x1f4 to 0x3ff from 0x000 to 0x20b n/a n/a 2% r-tolerance from 0x8c to 0x3ff from 0x000 to 0x373 from 0xb4 to 0x3ff from 0x000 to 0x34b from 0xfa to 0x3ff from 0x000 to 0x305 from 0xfa to 0x3ff from 0x000 to 0x305 3% r-tolerance from 0x5a to 0x3ff from 0x000 to 0x3a5 from 0x64 to 0x3ff from 0x000 to 0x39b from 0x78 to 0x3ff from 0x000 to 0x387 from 0x78 to 0x3ff from 0x000 to 0x387
ad5291/ad5292 rev. d | page 8 of 32 table 6. r ab = 50 k r ab = 100 k |v dd ? v ss | = 26 v to 33 v |v dd ? v ss | = 21 v to 26 v |v dd ? v ss | = 26 v to 33 v |v dd ? v ss | = 21 v to 26 v resistor tolerance per code r wb r wa r wb r wa r wb r wa r wb r wa 1% r-tolerance from 0x08c to 0x3ff from 0x000 to 0x35f from 0x0b4 to 0x3ff from 0x000 to 0x31e from 0x04b to 0x3ff from 0x000 to 0x3b4 from 0x064 to 0x3ff from 0x000 to 0x39b 2% r-tolerance from 0x03c to 0x3ff from 0x000 to 0x3c3 from 0x050 to 0x3ff from 0x000 to 0x3af from 0x028 to 0x3ff from 0x000 to 0x3d7 from 0x028 to 0x3ff from 0x000 to 0x3d7 3% r-tolerance from 0x028 to 0x3ff from 0x000 to 0x3d7 from 0x032 to 0x3ff from 0x000 to 0x3cd from 0x019 to 0x3ff from 0x000 to 0x3e6 from 0x019 to 0x3ff from 0x000 to 0x3e6 interface timing specifications v dd /v ss = 15 v, v logic = 2.7 v to 5.5 v, ?40c < t a < +105c. all specifications t min to t max , unless otherwise noted. table 7. parameter limit 1 unit description t 1 2 20 ns min sclk cycle time t 2 10 ns min sclk high time t 3 10 ns min sclk low time t 4 10 ns min sync to sclk falling edge setup time t 5 5 ns min data setup time t 6 5 ns min data hold time t 7 1 ns min sclk falling edge to sync rising edge t 8 400 3 ns min minimum sync high time t 9 14 ns min sync rising edge to next sclk fall ignore t 10 4 1 ns min rdy rising edge to sync falling edge t 11 4 40 ns max sync rising edge to rdy fall time t 12 4 2.4 s max rdy low time, rdac register write command execute time (r-perf mode) t 12 4 410 ns max rdy low time, rdac register write command execute time (normal mode) t 12 4 8 ms max rdy low time, memory program execute time t 12 4 1.5 ms min software/hardware reset t 13 4 450 ns max rdy low time, rdac register readback execute time t 13 4 1.3 ms max rdy low time, memory readback execute time t 14 4 450 ns max sclk rising edge to sdo valid t reset 20 ns min minimum reset pulse width (asynchronous) t power-up 5 2 ms max power-on otp restore time 1 all input signals are specified with t r = t f = 1 ns/v (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. 2 maximum sclk frequency is 50 mhz. 3 refer to t 12 and t 13 for rdac register and me mory commands operations. 4 r pull_up = 2.2 k to v logic , with a capacitance load of 168 pf. 5 maximum time after v logic is equal to 2.5 v. data bits db9 (msb) db0 (lsb) d7 d6 d5 d4 d3 d2 d1 d0 control bits c0c1 c2 d9 d8 c3 00 07674-003 figure 2. shift register content
ad5291/ad5292 rev. d | page 9 of 32 timing diagrams t 4 t 3 t 2 t 5 t 7 t 6 d0 d1 x sync sclk t 9 t 1 t 8 din sdo d6 d7 d2 xc3 c2 rdy t 12 t 10 t 11 07674-004 reset t reset figure 3. write timing diagram, cpol = 0, cpha = 1 d0 d1 x sync sclk t 9 t 14 t 13 t 11 din sdo x d0 x xc3 rdy d0 x x c3 d0 d1 c3 07674-005 figure 4. read timing diagram, cpol = 0, cpha = 1
ad5291/ad5292 rev. d | page 10 of 32 absolute maximum ratings t a = 25c, unless otherwise noted. table 8. parameter rating v dd to gnd ?0.3 v to +35 v v ss to gnd +0.3 v to ? 25 v v logic to gnd ?0.3 v to + 7 v v dd to v ss 35 v v a , v b , v w to gnd v ss ? 0.3 v, v dd + 0.3 v digital input and output voltage to gnd ?0.3 v to v logic + 0.3 v ext_cap voltage to gnd ?0.3 v to +7 v i a , i b , i w continuous r ab = 20 k 3 ma r ab = 50 k, 100 k 2ma pulsed 1 frequency > 10 khz mcc 2 /d 3 frequency 10 khz mcc 2 /d 3 operating temperature range 4 ?40c to +105c maximum junction temperature (t j max) 150c storage temperature range ?65c to +150c reflow soldering peak temperature 260c time at peak temperature 20 sec to 40 sec package power dissipation (t j max ? t a )/ ja stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is defined by jedec specification jesd-51 and the value is dependent on the test board and test environment. table 9. thermal resistance package type ja jc unit 14-lead tssop 93 1 20 c/w 1 jedec 2s2p test board, still air (0 m/sec to 1 m/sec air flow). esd caution 1 maximum terminal current is bounde d by the maximum current handling of the switches, maximum power dissip ation of the package, and maximum applied voltage across any two of the a, b, and w terminals at a given resistance. 2 maximum continuous current 3 pulse duty factor. 4 includes program ming of otp memory.
ad5291/ad5292 rev. d | page 11 of 32 pin configuration and fu nction descriptions reset v ss a w rdy sync v logic sclk b v dd ext_cap 1 2 3 4 5 6 7 din gnd 14 13 12 11 10 9 8 ad5291/ ad5292 top view not to scale sdo 07674-006 figure 5. pin configuration table 10. pin function descriptions pin o. mnemonic description 1 reset hardware reset pin. refreshes the rdac register with the contents of the 20-tp memory register. factory default loads midscale until the first 20-tp wiper memory location is programmed. reset is activated at the logic high transition. tie reset to v logic if not used. 2 v ss negative supply. connect to 0 v for single-supply applications. this pin should be decoupled with 0.1 f ceramic capacitors and 10 f capacitors. 3 a terminal a of rdac. v ss v a v dd . 4 w wiper terminal of rdac. v ss v w v dd . 5 b terminal b of rdac. v ss v b v dd . 6 v dd positive power supply. this pin should be decoupled with 0.1 f ceramic capacitors and 10 f capacitors. 7 ext_cap external capacitor. connect a 1 f capacitor to ext_cap. this capacitor must have a voltage rating of 7 v. 8 v logic logic power supply; 2.7 v to 5.5 v. this pin should be decoupled with 0.1 f ceramic capacitors and 10 f capacitors. 9 gnd ground pin, logic ground reference. 10 din serial data input. the ad5291 and ad5292 have a 16-bit shif t register. data is clocked into the register on the falling edge of the serial clock input. 11 sclk serial clock input. data is clocked into the shift register on the falling edge of the serial clock input. data can be transferred at rates up to 50 mhz. 12 sync falling edge synchronization signal. this is the frame synchronization signal for the input data. when sync goes low, it enables the shift register and data is transferred in on the falling edges of the following clocks. the selected register is updated on the rising edge of sync following the 16 th clock cycle. if sync is taken high before the 16 th clock cycle, the rising edge of sync acts as an interrupt, and the write sequence is ignored by the dac. 13 sdo serial data output. this open-drain o utput requires an external pull-up resi stor. sdo can be used to clock data from the shift register in daisy-chain mode or in readback mode. 14 rdy ready pin. this active-high open-drain output identifies th e completion of a write or read operation to or from the rdac register or memory.
ad5291/ad5292 rev. d | page 12 of 32 typical performance characteristics 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 0 128 256 384 512 640 768 896 1023 inl (lsb) code (decimal) +25c ?40c +105c 07674-106 r ab = 20k ? figure 6. r-inl in r-perf mode vs. code vs. temperature (ad5292) 0.6 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0 128 256 384 512 640 768 896 1023 dnl (lsb) code (decimal) +25c ?40c +105c 07674-007 r ab = 20k ? figure 7. r-dnl in r-perf mode vs. code vs. temperature (ad5292) 1.0 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 0 128 256 384 512 640 768 896 1023 inl (lsb) code (decimal) +25c ?40c +105c 07674-010 r ab = 20k ? figure 8. r-inl in normal mode vs. code vs. temperature (ad5292) 07674-215 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 0 128 256 384 512 640 768 896 1023 inl (lsb) code (decimal) 20k ? 50k ? 100k ? temperature = 2 5c figure 9. r-inl in r-perf mode vs. code vs. nominal resistance (ad5292) 07674-211 0.6 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0 128 256 384 512 640 768 896 1023 dnl (lsb) code (decimal) 20k ? 50k ? 100k ? temperature = 2 5c figure 10. r-dnl in r-perf mode vs. code vs. nominal resistance (ad5292) 07674-216 1.0 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 0 128 256 384 512 640 768 896 1023 inl (lsb) code (decimal) 20k ? 50k ? 100k ? temperature = 2 5c figure 11. r-inl in normal mode vs. code vs. nominal resistance (ad5292)
ad5291/ad5292 rev. d | page 13 of 32 0.15 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0 128 256 384 512 640 768 896 1023 dnl (lsb) code (decimal) +25c ?40c +105c 07674-011 r ab = 20k ? figure 12. r-dnl in normal mode vs . code vs. temper ature (ad5292) 1.5 ?1.5 ?1.0 ?0.5 0 0.5 1.0 0 128 256 384 512 640 768 896 1023 inl (lsb) code (decimal) +25c ?40c +105c 07674-014 r ab = 20k ? figure 13. inl in r-perf mode vs. code vs. temperature (ad5292) 0.6 0.5 0.4 0.3 0.2 0.1 0 ?0.2 ?0.1 0 128 256 384 512 640 768 896 1023 dnl (lsb) code (decimal) +25c ?40c +105c 07674-015 r ab = 20k ? figure 14. dnl in r-perf mode vs . code vs. temperature (ad5292) 07674-213 0.15 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0 128 256 384 512 640 768 896 1023 dnl (lsb) code (decimal) 20k ? 50k ? 100k ? temperature = 2 5c figure 15. r-dnl in normal mode vs. code vs. nominal resistance (ad5292) 07674-207 0.8 ?0.8 ?0.6 ?0.2 0 0.2 0.6 0 128 256 384 512 640 768 896 1023 inl (lsb) code (decimal) 20k ? 50k ? 100k ? temperature = 2 5c figure 16. inl in r-perf mode vs. code vs. nominal resistance (ad5292) 07674-203 0.6 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0 128 256 384 512 640 768 896 1023 dnl (lsb) code (decimal) 20k ? 50k ? 100k ? temperature = 2 5c figure 17. dnl in r-perf mode vs. co de vs. nominal resi stance (ad5292)
ad5291/ad5292 rev. d | page 14 of 32 0.8 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0 128 256 384 512 640 768 896 1023 inl (lsb) code (decimal) +25c ?40c +105c 07674-018 r ab = 20k ? figure 18. inl in normal mode vs . code vs. temperature (ad5292) 0.10 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0 128 256 384 512 640 768 896 1023 dnl (lsb) code (decimal) +25c ?40c +105c 07674-019 r ab = 20k ? figure 19. dnl in normal mode vs. code vs. temperature (ad5292) 0.30 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 0.25 0 32 64 96 128 160 192 224 255 inl (lsb) code (decimal) +25c ?40c +105c 07674-008 r ab = 20k ? figure 20. r-inl in r-perf mode vs. code vs. temperature (ad5291) 07674-209 0.8 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0 128 256 384 512 640 768 896 1023 inl (lsb) code (decimal) 20k? 50k? 100k ? temperature = 2 5c figure 21. inl in normal mode vs. co de vs. nominal resi stance (ad5292) 07674-205 0.08 ?0.16 ?0.12 ?0.08 ?0.04 0 0.04 0 128 256 384 512 640 768 896 1023 dnl (lsb) code (decimal) 20k ? 50k ? 100k ? temperature = 2 5c figure 22. dnl in normal mode vs. code vs. nominal resistance (ad5292) 0.30 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 0.25 0 32 64 96 128 160 192 224 255 inl (lsb) code (decimal) 20k? 50k? 100k ? 07674-218 temperature = 2 5c figure 23. r-inl in r-perf mode vs . code vs. nominal resistance (ad5291)
ad5291/ad5292 rev. d | page 15 of 32 0.14 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.10 0.12 0 32 64 96 128 160 192 224 255 dnl (lsb) code (decimal) +25c ?40c +105c 07674-009 r ab = 20k ? figure 24. r-dnl in r-perf mode vs . code vs. temperature (ad5291) 0.25 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 0 32 64 96 128 160 192 224 255 inl (lsb) code (decimal) +25c ?40c +105c 07674-012 r ab = 20k ? figure 25. r-inl in normal mode vs. code vs. temperature (ad5291) 0.03 ?0.05 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0 32 64 96 128 160 192 224 255 dnl (lsb) code (decimal) +25c ?40c +105c 07674-013 r ab = 20k ? figure 26. r-dnl in normal mode vs . code vs. temper ature (ad5291) 07674-212 0.14 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.10 0.12 0 32 64 96 128 160 192 224 255 dnl (lsb) code (decimal) 20k? 50k? 100k ? temperature = 2 5c figure 27. r-dnl in r-perf mode vs. code vs. nominal resistance (ad5291) 07674-217 0.25 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 0 32 64 96 128 160 192 224 255 inl (lsb) code (decimal) 20k? 50k? 100k ? temperature = 2 5c figure 28. r-inl in normal mode vs. code vs. nominal resistance (ad5291) 07674-214 0.03 ?0.05 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0 32 64 96 128 160 192 224 255 dnl (lsb) code (decimal) 20k? 50k? 100k ? temperature = 2 5c figure 29. r-dnl in normal mode vs. code vs. nominal resistance (ad5291)
ad5291/ad5292 rev. d | page 16 of 32 0.25 ?0.25 ?0.15 ?0.05 ?0.20 ?0.10 0 0.05 0.10 0.15 0.20 0 32 64 96 128 160 192 224 255 inl (lsb) code (decimal) +25c ?40c +105c 07674-016 r ab = 20k ? figure 30. inl in r-perf mode vs. code vs. temperature (ad5291) 0.14 ?0.06 ?0.02 0.02 ?0.04 0 0.04 0.06 0.08 0.10 0.12 0 32 64 96 128 160 192 224 255 dnl (lsb) code (decimal) +25c ?40c +105c 07674-017 r ab = 20k ? figure 31. dnl in r-perf mode vs . code vs. temperature (ad5291) 0.20 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0 32 64 96 128 160 192 224 256 inl (lsb) code (decimal) +25c ?40c +105c 07674-020 figure 32. inl in normal mode vs . code vs. temperature (ad5291) 07674-208 0.25 ?0.25 ?0.15 ?0.05 ?0.20 ?0.10 0 0.05 0.10 0.15 0.20 0 32 64 96 128 160 192 224 255 inl (lsb) code (decimal) 20k? 50k? 100k ? temperature = 2 5c figure 33. inl in r-perf mode vs. co de vs. nominal resistance (ad5291) 07674-204 0.14 ?0.06 ?0.02 0.02 ?0.04 0 0.04 0.06 0.08 0.10 0.12 0 32 64 96 128 160 192 224 255 dnl (lsb) code (decimal) 20k ? 50k ? 100k ? temperature = 2 5c figure 34. dnl in r-perf mode vs. co de vs. nominal resi stance (ad5291) 07674-210 0.20 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0 32 64 96 128 160 192 224 255 inl (lsb) code (decimal) 20k? 50k? 100k ? temperature = 2 5c figure 35. inl in normal mode vs. co de vs. nominal resi stance (ad5291)
ad5291/ad5292 rev. d | page 17 of 32 0.03 ?0.05 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0 32 64 96 128 160 192 224 255 dnl (lsb) code (decimal) +25c ?40c +105c 07674-021 r ab = 20k ? figure 36. dnl in normal mode vs. code vs. temperature (ad5291) 07674-022 450 400 350 300 250 200 150 100 50 0 ?50 supply current (na) temperature (c) ?40?30?20?100 102030405060708090100 i logic v dd /v ss = 15v v logic = +5v i dd i ss figure 37. supply current (i dd , i ss , i logic ) vs. temperature 700 600 500 400 300 200 100 0 rheostat mode tempco (ppm/c) 07674-024 0 256 512 768 1023 0 64 128 192 255 ad5292 ad5291 code (decimal) 50k ? 20k ? 100k? v dd = 30v, v ss = 0v figure 38. rheostat mode tempco r wb /t vs. code 07674-206 0.03 ?0.05 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0 32 64 96 128 160 192 224 255 dnl (lsb) code (decimal) 20k ? 50k ? 100k ? temperature = 2 5c figure 39. dnl in normal mode vs. code vs. temperature (ad5291) 07674-031 0.20 0.18 0.16 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 supply current i logic (ma) digital input voltage (v) v dd = 15v figure 40. supply current i logic vs. digital input voltage 700 600 500 400 300 200 100 0 potentiometer mode tempco (ppm/c) 07674-023 0 256 512 768 1023 0 64 128 192 255 ad5292 ad5291 code (decimal) v dd = 30v v ss = 0v 50k? 20k? 100k ? figure 41. potentiometer mode tempco r wb /t vs. code
ad5291/ad5292 rev. d | page 18 of 32 0 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 1m 100k 10k 1k 100 10 07674-025 gain (db) frequency (hz) ad5292 (ad5291) 0x200 (0x80) 0x100 (0x40) 0x080 (0x20) 0x040 (0x10) 0x020 ( 0x08) 0x010 (0x04) 0x008 (0x02) 0x004 (0x01) 0x002 0x001 figure 42. 20 k gain vs. frequency vs. code ?50 ?40 ?30 ?10 0 10 1m 100k 10k 1k 100 gain (db) frequency (hz) 0x200 (0x80) 0x080 (0x20) 0x020 ( 0x08) 0x010 (0x04) 0x004 (0x01) 0x002 0x001 ad5292 (ad5291) ?20 ?60 07674-200 0x040 (0x10) 0x008 (0x02) 0x100 (0x40) figure 43. 50 k gain vs. frequency vs. code 07674-027 0 ?120 ?105 ?90 ?75 ?60 ?45 ?30 ?15 thd + n (db) frequency (hz) 100 1k 10k 100k v dd /v ss = 15v code = half scale v in = 1v rms noise bw = 22khz 50k ? 20k ? 100k ? figure 44. thd + noise vs. frequency ?65 ?60 ?50 ?45 ?40 ?35 ?30 ?25 ?15 ?10 ?5 0 11 100k 10k 1k 100 10 gain (db) frequency (hz) m 0x200 (0x80) 0x100 (0x40) 0x080 (0x20) 0x040 (0x10) 0x020 ( 0x08) 0x010 (0x04) 0x008 (0x02) 0x004 (0x01) 0x002 0x001 ad5292 (ad5291) ?20 ?55 ?67.5 07674-201 figure 45. 100 k gain vs. frequency vs. code ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 100 1k 10k frequency (hz) 100k 1m 100k ? 20k ? 50k ? 07674-026 psrr (db) figure 46. power supply reje ction ratio vs. frequency ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0.001 0.01 0.1 1 10 thd + n (db) amplitude (v rms) 07674-220 v dd /v ss = 15v, code = half scale f in = 1khz noise bw = 22khz 50k ? 20k ? 100k ? figure 47. thd + noise vs. amplitude
ad5291/ad5292 rev. d | page 19 of 32 0 100,000 200,000 300,000 400,000 500,000 600,000 700,000 bandwidth (hz) 800,000 900,000 1,000,000 code (decimal) 512 0 128 64 32 16 8 0 128 256 64 32 16 8 07674-222 20k ? 0pf 20k ? 75pf 20k ? 150pf 20k ? 250pf 50k ? 0pf 50k ? 75pf 50k ? 150pf 50k ? 250pf 100k ? 0pf 100k ? 75pf 100k ? 150pf 100k ? 250pf ad5292 ad5291 figure 48. bandwidth vs code vs net capacitance 07674-034 35 30 25 ?5 20 15 10 5 0 ?0.4 1.2 1.0 0.8 0.6 0.4 0.2 0 ?0.2 supply current i dd (ma) time (ms) figure 49. i dd waveform while blowing/reading fuse 07674-033 35 ?5 0 5 10 15 20 25 30 voltage (v) time (s) v wb , code: full scale, normal mode sync ?2 ?1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 v dd /v ss = 30v/0v v logic = 5v v a = v dd v b = v ss v wb , code: half-scale, normal mode v wb , code: half-scale, r-perf mode 20k 50k 100k 20k 50k 100k v wb , code: full scale, r-perf mode figure 50. 20k large-signal settling time from code zero scale 8 0 1 2 3 4 5 6 7 0 256 512 768 1023 0 64 128 192 255 ad5292 ad5291 theoretical i wb_max (ma) code (decimal) 07674-029 v dd /v ss = 30v/0v v a = v dd v b = v ss 50k 20k 100k figure 51. theoretical maximum current vs. code 07674-035 1.2 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 voltage (v) time (s) ?2 0 2 4 6 8 10 12 14 16 v dd /v ss = 15v v logic = +5v v a = v dd v b = v ss 50k 20k 100k figure 52. maximum transition glitch 40 32 24 ? 40 ?32 ?24 ?16 ?8 0 8 16 ?0.5 0 5 10 15 20 25 30 35 40 45 voltage ( v) time (s) v dd /v ss = 15v v a = v dd v b = v ss code = half code 07674-032 figure 53. digital feedthrough
ad5291/ad5292 rev. d | page 20 of 32 07674-056 number of codes (ad5292) 300 250 200 150 100 50 0 number of codes (ad5291) 75.0 62.5 50.0 37.5 25.0 12.5 0 temperature (c) ?40?30?20?100 102030405060708090100 v dd /v ss = 15v 50k? 20k? 100k ? 07674-036 6 0 ?1 1 2 3 4 5 voltage (v) time (ms) v dd /v ss = 15v v logic = +5v ?1.0 ?0.4 0.2 0.8 1.4 2.0 2.6 3.2 3.8 4.4 5.0 5.6 6.2 6.8 7.4 8.0 8.6 figure 54. v ext_cap waveform while reading fuse or calibration figure 56. code range > 1% r-tolerance error vs. temperature 07674-037 8 ?2 0 2 3 6 voltage (v) time (ms) v dd /v ss = 15v v logic = +5v ?2.0 ?0.8 0.4 1.6 2.8 4.0 5.2 6.4 7.6 8.8 10.0 11.2 12.4 13.6 14.8 16.0 17.2 20.0 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 21 26 30 33 voltage v dd /v ss number of codes (ad5292) number of codes (ad5291) 80 0 10 20 30 40 50 60 70 07674-219 v a = v dd v b = v ss temperature = 25c 50k ? 20k ? 100k ? figure 57. code range > 1% r-tolerance error vs. voltage figure 55. v ext_cap waveform while writing fuse
ad5291/ad5292 rev. d | page 21 of 32 test circuits figure 58 to figure 63 define the test conditions used in the specifications section. a w b nc i w dut v ms nc = no connect 07674-041 figure 58. resistor position nonlinearity error (rheostat operation; r-inl, r-dnl) a w b dut v ms v+ v + = v dd 1lsb = v+/2 n 07674-042 figure 59. potentiometer divider nonlinearity error (inl, dnl) + ? dut code = 0x00 0.1v v ss to v dd r wb = 0.1 v i wb r w = r wb 2 i wb w b a = nc 0 7674-043 figure 60. wiper resistance a w b v ms ~ v a v dd v+ v+ = v dd 10% ? v ms % ? v dd % pss (%/%) = psrr (db) = 20 log ? v ms ? v dd 07674-044 figure 61. power supply sensitivity (pss, psrr) offset gnd a b dut w +15 v v in v out op42 ?15v 2.5v 0 7674-047 figure 62. gain vs. frequency v ss i cm w b v dd dut gnd a nc = no connect nc ?15v gnd +15v nc +15 v +15v ?15v ?15v gnd gnd gnd 07674-048 figure 63. common-mode leakage current
ad5291/ad5292 rev. d | page 22 of 32 theory of operation the ad5291 and ad5292 digital potentiometers are designed to operate as true variable resistors for analog signals that remain within the terminal voltage range of v ss < v term < v dd . the patented 1% resistor tolerance feature helps to minimize the total rdac resistance error, which reduces the overall system error by offering better absolute matching and improved open-loop performance. the digital potentiometer wiper position is determined by the rdac register contents. the rdac register acts as a scratchpad register, allowing as many value changes as necessary to place the potentiometer wiper in the correct position. the rdac register can be programmed with any position setting using the standard spi interface by loading the 16-bit data-word. once a desirable position is found, this value can be stored in a 20-tp memory register. thereafter, the wiper position is always restored to that position for subsequent power- up. the storing of 20-tp data takes approximately 6 ms; during this time, the shift register is locked, preventing any changes from taking place. the rdy pin identifies the completion of this 20- tp storage. serial data interface the ad5291 and ad5292 contain a serial interface ( sync , sclk, din and sdo) that is compatible with spi interface standards, as well as most dsps. the part allows writing of data via the serial interface to every register. shift register the ad5291 and ad5292 shift register is 16 bits wide (see figure 2 ). the 16-bit input word consists of two unused bits (set to 0), followed by four control bits, and 10 rdac data bits. for the ad5291, the lower two rdac data bits are dont cares if the rdac register is read from or written to. data is loaded msb first (bit db15). the four control bits determine the function of the software command (see table 11 ). figure 3 shows a timing diagram of a typical ad5291 and ad5292 write sequence. the write sequence begins by bringing the sync line low. the sync pin must be held low until the complete data-word is loaded from the din pin. when sync returns high, the serial data-word is decoded according to the commands in . the command bits (cx) control the operation of the digital potentiometer. the data bits (dx) are the values that are loaded into the decoded register. the ad5291 and ad5292 have an internal counter that counts a multiple of 16 bits (a frame) for proper operation. for example, ad5291 and ad5292 work with a 32-bit word but does not work properly with a 31-bit or 33-bit word. the ad5291 and ad5292 do not require a continuous sclk, when table 11 sync is high, and all serial interface pins should be operated at close to the v logic supply rails to minimize power consumption in the digital input buffers. rdac register the rdac register directly controls the position of the digital potentiometer wiper. for example, when the rdac register is loaded with all zeros, the wiper is connected to terminal b of the variable resistor. the rdac register is a standard logic register; there is no restriction on the number of changes allowed. table 11. command operation truth table command bits [db13:db10] data bits [db9:db0] 1 command c3 c2 c1 c0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 operation 0 0 0 0 0 x x x x x x x x x x nop command: do nothing. 1 0 0 0 1 d9 d8 d7 d6 d5 d4 d3 d2 d1 2 d0 2 write contents of serial data to rdac. 2 0 0 1 0 x x x x x x x x x x read rdac wiper setting from the sdo output in the next frame. 3 0 0 1 1 x x x x x x x x x x store wiper setting: store rdac setting to 20-tp memory. 4 0 1 0 0 x x x x x x x x x x reset: refresh rdac with 20-tp stored value. 5 0 1 0 1 x x x x x d4 d3 d2 d1 d0 read contents of 20-tp memory, or status of 20-tp memory, from the sdo output in the next frame. 6 0 1 1 0 x x x x x x d3 d2 d1 d0 write contents of serial data to control register. 7 0 1 1 1 x x x x x x x x x x read control register from the sdo output in the next frame. 8 1 0 0 0 x x x x x x x x x d0 software shutdown. d0 = 0 (normal mode). d0 = 1 (device placed in shutdown mode). 1 x = dont care. 2 in the ad5291, this bit is a dont care.
ad5291/ad5292 rev. d | page 23 of 32 20-tp memory once a desirable wiper position is found, the contents of the rdac register can be saved into a 20-tp memory register (see table 12 ). thereafter, the wiper position is always set at that position for any future on-off-on power supply sequence. the ad5291 and ad5292 have an array of 20 one-time programmable (otp) memory registers. when the desired word is programmed to 20-tp memory, the device automatically verifies that the program command was successful. the verification process includes margin testing. bit c3 of the control register can be polled to verify that the fuse program command was successful. programming data to 20-tp memory consumes approximately 25 ma for 550 s and takes approximately 8 ms to complete. during this time, the shift register is locked, preventing any changes from taking place. the rdy pin can be used to monitor the completion of the 20-tp memory program and verification. no change in supply voltage is required to program the 20-tp memory. however, a 1 f capacitor on the ext_cap pin is required (see figure 68 ). prior to 20-tp activation, the ad5291 and ad5292 preset to midscale on power-up. write protection on power-up, the shift register write commands for both the rdac register and the 20-tp memory register are disabled. the rdac write protect bit, c1 of the control register (see table 13 and table 14 ), is set to 0 by default. this disables any change of the rdac register content regardless of the software commands, except that the rdac register can be refreshed from the 20-tp memory using the software reset command (command 4) or through hardware by the reset pin. to enable programming of the variable resistor wiper position (program- ming the rdac register), the write protect bit, c1 of the control register, must first be programmed. this is accomplished by loading the shift register with command 6 (see ). to enable programming of the 20-tp memory block bit, c0 of the control register (set to 0 by default) must first be set to 1. table 11 table 12. write and read to rdac and 20-tp memory din sdo action 0x1803 0xxxxx enable update of wiper position and 20- tp memory contents through digital interface. 0x0500 0x1803 write 0x100 to the rdac register; wiper moves to ? full-scale position. 0x0800 0x0500 prepare data read from the rdac register. 0x0c00 0x0100 stores rdac register content into 20-tp memory. the 16- bit word appears out of sdo, where the last 10 bits contain the contents of the rdac register (0x100). 0x1c00 0x0c00 prepare data read from the control register. 0x0000 0x000x nop instruction 0 sends 16-bit word out of sdo, where th e last four bits contain the contents of the control register. if bit c3 = 1, the fuse program command is successful. table 13. control register bit map 1 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 x x x x x x c3 c2 c1 c0 1 x = dont care. table 14. control register function bit name description c0 20-tp program enable 0 = 20-tp program disabled (default) 1 = enable device for 20-tp program c1 rdac register write protect 0 = wiper position frozen to value in memory (default) 1 1 = allow update of wiper position through digital interface c2 calibration enable 0 = resistor performance mode enabled (default) 1 = normal mode enabled c3 20-tp memory program success 0 = fuse program command unsuccessful (default) 1 = fuse program command successful 1 wiper position frozen to value last programmed in 20-tp memory. wiper is froz en to midscale if 20-tp memory has not been previ ously programmed.
ad5291/ad5292 rev. d | page 24 of 32 basic operation the basic mode of setting the variable resistor wiper position (programming the rdac register) is accomplished by loading the shift register with command 1 (see table 11 ) and the desired wiper position data. when the desired wiper position is deter- mined, the user can load the shift register with command 3 (see table 11 ), which stores the wiper position data in the 20-tp memory register. after 6 ms, the wiper position is permanently stored in the 20-tp memory. the rdy pin can be used to moni- tor the completion of this 20-tp program. tabl e 12 provides a programming example, listing the sequence of serial data input (din) words with the serial data output appearing at the sdo pin in hexadecimal format. 20-tp readback and spare memory status it is possible to read back the contents of any of the 20-tp memory registers through sdo by using command 5 (see table 11 ). the lower five lsb bits (d0 to d4) of the data byte select which memory location is to be read back (see table 16 ). data from the selected memory location are clocked out of the sdo pin during the next spi operation, where the last 10 bits contain the contents of the specified memory location. it is also possible to calculate the address of the most recently programmed memory location by reading back the contents of read-only memory address 0x14 and memory address 0x15 using command 5. the data bytes read back from memory address 0x014 and memory address 0x015 are thermometer encoded versions of the address of the last programmed memory location. for the example outlined in table 15 , the address of the last programmed location is calculated as ( number of bits = 1 in memory address 0x14 ) + ( number of bits = 1 in memory address 0x15 ) ? 1 = 10 + 8 ? 1 = 17 (0x10) if no memory location has been programmed, then the address generated is ?1. shutdown mode the ad5291 and ad5292 can be placed in shutdown mode by executing the software shutdown command, command 8 (see table 11 ), and setting the lsb, d0, to 1. this feature places the rdac in a special state in which terminal a is open-circuited, and wiper w is connected to terminal b. the contents of the rdac register are unchanged by entering shutdown mode. however, all commands listed in table 11 are supported while in shutdown mode. execute command 8 (see table 11 ), and set the lsb, d0, to 0 to exit shutdown mode. table 15. example 20-tp memory readback din sdo action 0x1414 0xxxxx prepares data read from memory address 0x14. 0x1415 0x03ff prepares data read from memory address 0x15. sends 16-bit word out of sdo, where the last 10 bits contain the contents of memory address 0x14. 0x0000 0x00ff nop command 0 sends 16-bit word out of sdo, where last 10-bits contain the contents of memory address 0x15. 0x1410 0x0000 prepares data read from memory location 0x10. 0x0000 0xxxxx nop instruction 0 sends 16-bit word out of sdo, where the last 10 bits contain the contents of memory address 0x1 0 (17). table 16. memory map of command 5 data bits [db9:db0] 1 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 register contents x x x x x 0 0 0 0 0 1 st programmed wiper location (0x00) x x x x x 0 0 0 0 1 2 nd programmed wiper location (0x01) x x x x x 0 0 0 1 0 3 rd programmed wiper location (0x02) x x x x x 0 0 0 1 1 4 th programmed wiper location (0x03) x x x x x 0 0 1 0 0 5 th programmed wiper location (0x04) x x x x x 0 1 0 0 1 10 th programmed wiper location (0x09) x x x x x 0 1 1 1 0 15 th programmed wiper location (0x0e) x x x x x 1 0 0 1 1 20 th programmed wiper location (0x13) x x x x x 1 0 1 0 0 programmed memo ry status (thermometer encoded) 2 (0x14) x x x x x 1 0 1 0 1 programmed memo ry status (thermometer encoded) 2 (0x15) 1 x = dont care. 2 allows the user to calculate the remaining spare memory locations.
ad5291/ad5292 rev. d | page 25 of 32 resistor performance mode this mode activates a new, patented 1% end-to-end resistor tolerance that ensures a 1% resistor tolerance on each code, that is, code = half scale, r wb = 10 k 100 . see table 2 (ad5291) or table 5 (ad5292) to check which codes achieve 1% resistor tolerance. the resistor performance mode is activated by programming bit c2 of the control register (see table 13 and table 14 ). the typical settling time is shown in figure 50 . reset a low-to-high transition of the hardware reset pin loads the rdac register with the contents of the most recently programmed 20-tp memory location. the ad5291 and ad5292 can also be reset through software by executing command 4 (see ). if no 20-tp memory location is programmed, then the rdac register loads with midscale upon reset. the control register is restored with default bits; see . table 11 table 14 sdo pin and daisy-chain operation the serial data output pin (sdo) serves two purposes: it can be used to read the contents of the wiper setting, 50-tp values and control register using command 2, command 5 and command 7, respectively (see table 11 ) or the sdo pin can be used in daisy- chain mode. data is clocked out of sdo on the rising edge of sclk. the sdo pin contains an open-drain n-channel fet that requires a pull-up resistor if this pin is used. to place the pin in high impedance and minimize the power dissipation when the pin is used, the 0x8001 data word followed by command 0 should be sent to the part. tabl e 1 7 provides a sample listing for the sequence of the serial data input (din). daisy chaining minimizes the number of port pins required from the controlling ic. as shown in figure 64 , users need to tie the sdo pin of one package to the din pin of the next package. users may need to increase the clock period, because the pull-up resistor and the capacitive loading at the sdo-to- din interface may require additional time delay between subsequent devices. when two ad5291 and ad5292 devices are daisy-chained, 32 bits of data are required. the first 16 bits go to u2, and the second 16 bits go to u1. hold the sync pin low until all 32 bits are clocked into their respective shift registers. the sync pin is then pulled high to complete the operation. keep the sync pin low until all 32 bits are clocked into their respective serial registers. the sync pin is then pulled high to complete the operation. din sdo sclk sclk r p 2.2k ? din sdo u1 u2 ad5291/ ad5292 ad5291/ ad5292 sync v logic micro- controller sclk ss mosi sync 07674-050 figure 64. daisy-chain configuration using sdo rdac architecture to achieve optimum performance, analog devices has patented the rdac segmentation architecture for all the digital potentiometers. in particular, the ad5291 and ad5292 employ a three-stage segmentation approach, as shown in figure 65 . the ad5291 and ad5292 wiper switches are designed with the transmission gate cmos topology and with the gate voltages derived from v dd and v ss . r w s w w r w 8-/10-bit address decoder a r l r l r m r m b r m r m r l r l 07674-051 figure 65. simplified rdac circuit table 17. minimize power dissipation at sdo pin din sdo 1 action 0xxxxx 0xxxxx last user command sent to the digipot 0x8001 0xxxxx prepares the sdo pin to be placed in high impedance mode 0x0000 high impedance the sdo pin is placed in high impedance 1 x is dont care.
ad5291/ad5292 rev. d | page 26 of 32 programming the variable resistor rheostat operation1% resistor tolerance the ad5291 and ad5292 operate in rheostat mode when only two terminals are used as a variable resistor. the unused terminal can be left floating or tied to the w terminal, as shown in figure 66 . w a b w a b w a b 07674-052 figure 66. rheostat mode configuration the nomin a l resist anc e b e twe e n ter min a l a and ter min a l b, r ab , is available in 20 k, 50 k, and 100 k, and 256 or 1024 tap points accessed by the wiper terminal. the 8-/10-bit data in the rdac latch is decoded to select one of the 256/1024 possible wiper settings. the ad5291 and ad5292 contain an internal 1% resistor performance mode that can be disabled or enabled (this is enabled by default), by programming bit c2 of the control register (see table 1 3 and table 14 ). the digitally programmed output resistance between the w terminal and the a terminal, r wa , and between the w terminal and b terminal, r wb , is internally calibrated to give a maximum of 1% absolute resistance error across a wide code range. as a result, the general equations for determining the digitally programmed output resistance between the w terminal and b terminal are ad5291: ab wb r d dr = 256 )( (1) ad5292: ab wb r d dr = 1024 )( (2) where: d is the decimal equivalent of the binary code loaded in the 8-/10-bit rdac register. r ab is the end-to-end resistance. similar to the mechanical potentiometer, the resistance of the rdac between the w terminal and the a terminal also produces a digitally controlled complementary resistance, r wa . r wa is also calibrated to give a maximum of 1% absolute resistance error. r wa starts at the maximum resistance value and decreases as the data loaded into the latch increases. the general equations for this operation are ad5291: ab wa r d dr ? = 256 256 )( (3) ad5292: ab wa r d dr ? = 1024 1024 )( (4) where: d is the decimal equivalent of the binary code loaded in the 8-/10-bit rdac register. r ab is the end-to-end resistance. in the zero-scale condition, a finite total wiper resistance of 120 is present. regardless of which setting the part is operating in, take care to limit the current between terminal a and terminal b, between terminal w and terminal a, and between terminal w and terminal b, to the maximum continuous current of 3 ma or to the pulse current specified in table 8 . otherwise, degradation or possible destruction of the internal resistors may occur. programming the potentiometer divider voltage output operation the digital potentiometer easily generates a voltage divider at the wiper to b and at the wiper to a that is proportional to the input voltage at a to b, as shown in figure 67 . unlike the polarity of v dd to gnd, which must be positive, voltage across a to b, w to a, and w to b can be at either polarity. w a b v in v out 07674-053 figure 67. potentiometer mode configuration if ignoring the effect of the wiper resistance for simplicity, con- necting the a terminal to 30 v and the b terminal to ground produces an output voltage at the wiper w to terminal b ranging from 0 v to 1 lsb less than 30 v. each lsb of voltage is equal to the voltage applied across terminal a and terminal b, divided by the 256/1024 positions of the potentiometer divider. the general equations defining the output voltage at v w with respect to ground for any valid input voltage applied to terminal a and terminal b are ad5291: b a w v d v d dv ? += 256 256 256 )( (5) ad5292: b a w v d v d dv ? += 1024 1024 1024 ) ( (6) if using the ad5291 and ad5292 in voltage divider mode as shown in figure 67 , then the 1% resistor tolerance calibration feature reduces the error when matching with discrete resistors. however, it is recommended to disable the internal 1% resistor tolerance calibration feature by programming bit c2 of the control register (see table 13 and table 14 ) to optimize wiper position update rate. in this configuration, the rdac is ratiome- tric and resistor tolerance error does not affect performance.
ad5291/ad5292 rev. d | page 27 of 32 operation of the digital potentiometer in the voltage divider mode results in a more accurate operation over temperature. unlike the rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistors, r wa and r wb , and not the absolute values. therefore, the temperature drift reduces to 5 ppm/c. the ground pins of the ad5291 and ad5292 devices are primarily used as a digital ground reference. to minimize the digital ground bounce, the ad5291 and ad5292 ground terminals should be joined remotely to the common ground. the digital input control signals to the ad5291 and ad5292 must be referenced to the device ground pin (gnd), and satisfy the logic level defined in the specifications section. ext_cap capacitor power-up sequence a 1 f capacitor to gnd must be connected to the ext_cap pin (see figure 68 ) on power-up and throughout the operation of the ad5291 and ad5292. to ensure that the ad5291 and ad5292 power up correctly, a 1 f capacitor must be connected to the ext_cap pin. because there are diodes to limit the voltage compliance at terminal a, ter mina l b, and ter mina l w ( s e e figure 69 ), it is important to power v dd and v ss first before applying any voltage to terminal a, terminal b, and terminal w. otherwise, the diode is forward- biased such that v dd and v ss are powered up unintentionally. the ideal power-up sequence is gnd, v ss , v logic and v dd , the digital inputs, and then v a , v b , and v w . the order of powering up v a , v b , v w , and the digital inputs is not important as long as they are powered after v dd , v ss , and v logic . ad5291/ ad5292 gnd c1 1f otp memory block 07674-054 ext_cap figure 68. hardware setup for ext_cap pin terminal voltage operating range regardless of the power-up sequence and the ramp rates of the power supplies, after v logic is powered, the power-on preset activates, restoring the 20-tp memory value to the rdac register. the positive v dd and negative v ss power supplies of the ad5291 and ad5292 define the boundary conditions for proper 3-terminal digital potentiometer operation. supply signals present on terminal a, terminal b, and terminal w that exceed v dd or v ss are clamped by the internal forward- biased diodes (see figure 69 ). v ss v dd a w b 07674-055 figure 69. maximum terminal voltages set by v dd and v ss
ad5291/ad5292 rev. d | page 28 of 32 applications information high voltage dac the ad5292 can be configured as a high voltage dac, with output voltage as high as 33 v. the circuit is shown in figure 70 . the output is ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? += 1 2 1v2.1 1024 )( r r d dv out (7) where d is the decimal code from 0 to 1023. 07674-153 ad5292 u2 ad8512 v+ v? ad8512 v out v dd u1b v dd r bias a dr512 d1 r 2 r 1 b 20k u1a figure 70. high voltage dac programmable voltage source with boosted output for applications that require high current adjustments such as a laser diode or tunable laser, a boosted voltage source can be considered; see figure 71 . 07674-155 w signal c c r bias ld v in a b v out u1 ad5292 u3 2n7002 u2 i l op184 figure 71. programmable boosted voltage source in this circuit, the inverting input of the op amp forces v out to be equal to the wiper voltage set by the digital potentiometer. the load current is then delivered by the supply via the n-channel fet (u3). the n-channel fet power handling must be adequate to dissipate (v in ? v out ) i l power. this circuit can source a maximum of 100 ma with a 33 v supply. high accuracy dac it is possible to configure the ad5292 as a high accuracy dac by optimizing the resolution of the device over a specific reduced voltage range. this is achieved by placing external resistors on either side of the rdac, as shown in figure 72 . the improved 1% r-tolerance specification greatly reduces error associated with matching to discrete resistors. 3 1024 )1024( 1 1024 3 )( )( )( rr r vr r dv ab d dd ab d out + + + = ? (8) 07674-154 ad5292 u1 v out b r 2 20k r 1 r 3 1% op1177 v+ v? v dd v dd u2 figure 72. optimizing resolution variable gain instrumentation amplifier the ad8221 in conjunction with the ad5291 and ad5292 and the adg1207 , as shown in figure 73 , make an excellent instrumentation amplifier for use in data acquisition systems. the data acquisition systems low distortion and low noise enable it to condition signals in front of a variety of adcs. 07674-156 ad8221 ad5292 +v in1 v dd v ou t v ss a dg1207 +v in4 ?v in1 ?v in4 figure 73. data acquisition system the gain can be calculated by using equation 9. () ab rd dg += 1024 k 4.49 1)( (9)
ad5291/ad5292 rev. d | page 29 of 32 audio volume control the excellent thd performance and high voltage capability make the ad5291 and ad5292 ideal for a digital volume control as an audio attenuator or gain amplifier. a typical problem in these systems is that a large step change in the volume level at any arbitrary time can lead to an abrupt discontinuity of the audio signal causing an audible zipper noise. to prevent this, a zero-crossing window detector can be inserted to the sync line to delay the device update until the audio signal crosses the window. because the input signal can operate on top of any dc level rather than absolute zero volt level, zero-crossing in this case means the signal is ac-coupled, and the dc offset level is the signal zero reference point. the configuration to reduce zipper noise is shown in figure 74 , and the results of using this configuration is shown in figure 75 . the input is ac-coupled by c1 and attenuated down before feeding into the window comparator formed by u2, u3, and u4b. u6 is used to establish the signal zero reference. the upper limit of the comparator is set above its offset and, therefore, the output pulses high whenever the input falls between 2.502 v and 2.497 v (or 0.005 v window) in this example. this output is anded with the sync signal such that the ad5291 and ad5292 updates whenever the signal crosses the window. to avoid a constant update of the device, the sync signal should be programmed as two pulses, rather than as one. in figure 75 , the lower trace shows that the volume level changes from a quarter-scale to full-scale when a signal change occurs near the zero-crossing window. 07674-157 r 1 100k ? r 2 200 ? 5v v in v+ v? ad8541 5v u6 r 3 100k ? r 4 90k ? r 5 10k? c1 1f v dd v ss sclk sdin v+ v? ad5292 20k ? +15v ?15v c3 0.1f c2 0.1f a b w gnd sdin sclk u1 v cc gnd v cc gnd adcmp371 adcmp371 +15v ?15v +5v +5v u3 u2 v ou t u5 u4a u4b 16 2 4 5 7408 7408 sync sync figure 74. audio volume control with zipper noise reduction 0 7674-158 channel 1 freq = 20.25khz 1.03v p-p 1 2 figure 75. zipper noise detector
ad5291/ad5292 rev. d | page 30 of 32 outline dimensions compliant to jedec standards mo-153-ab-1 061908-a 8 0 4.50 4.40 4.30 14 8 7 1 6.40 bsc pin 1 5.10 5.00 4.90 0.65 bsc 0.15 0.05 0.30 0.19 1.20 max 1.05 1.00 0.80 0.20 0.09 0.75 0.60 0.45 coplanarity 0.10 seating plane figure 76. 14-lead thin shrink small outline package [tssop] (ru-14) dimensions shown in millimeters ordering guide model 1 r ab (k) resolution memory temperature ra nge package description package option ad5291bruz-20 20 256 20-tp ?40c to +105c 14-lead tssop ru-14 ad5291bruz-20-rl7 20 256 20-tp ?40c to +105c 14-lead tssop ru-14 ad5291bruz-50 50 256 20-tp ?40c to +105c 14-lead tssop ru-14 ad5291bruz-50-rl7 50 256 20-tp ?40c to +105c 14-lead tssop ru-14 ad5291bruz-100 100 256 20-tp ?40c to +105c 14-lead tssop ru-14 ad5291bruz-100-rl7 100 256 20-tp ?40c to +105c 14-lead tssop ru-14 ad5292bruz-20 20 1,024 20-tp ?40c to +105c 14-lead tssop ru-14 ad5292bruz-20-rl7 20 1,024 20-tp ?40c to +105c 14-lead tssop ru-14 ad5292bruz-50 50 1,024 20-tp ?40c to +105c 14-lead tssop ru-14 ad5292bruz-50-rl7 50 1,024 20-tp ?40c to +105c 14-lead tssop ru-14 ad5292bruz-100 100 1,024 20-tp ?40c to +105c 14-lead tssop ru-14 AD5292BRUZ-100-RL7 100 1,024 20-tp ?40c to +105c 14-lead tssop ru-14 eval-ad5292ebz evaluation board 1 z = rohs compliant part.
ad5291/ad5292 rev. d | page 31 of 32 notes
ad5291/ad5292 rev. d | page 32 of 32 notes ?2009C2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d07674-0-9/10(d)

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